1. Field of the Invention
The present invention relates to minimizing clock skews by current mode signals. More particularly, the present invention relates to minimizing clock skews by current mode signals and changing apparent line lengths and transmission time delays.
2. Discussion of the Related Art
Clock distribution is rapidly becoming one of the dominant design problems due to the increasing die sizes and clock frequencies, even for clock frequencies below 1 GHz. Since the speed of integrated circuits is expected to eventually reach above 10 GHZ, radically different on-chip interconnection and clock distribution schemes will be needed. Consideration has been given to both wireless and optical clock distribution. Wireless communication is described by K. Khong and K. O. Kenneth, xe2x80x9cCharacteristics of Integrated Dipole Antennas on Bulk, SOI and SOS Substrates for Wireless Communicationxe2x80x9d, Int. Interconnect Technology Conf., San Francisco, Calif., June 1998, pp. 21-23. Also, U.S. Pat. No. 5,812,708 discloses a method and apparatus for distributing an optical clock in an integrated circuit.
The problem with current techniques is that most clock distribution is achieved by voltage signals on RC lines and on capacitance dominated lines. As shown in FIGS. 1A and 1B, the delay (tdelay) in the clocking step signal (Vdriver(t)) is limited by the RC time constant of the distribution line 20 if the line is high resistance polysilicon, or the RC time constant of the driver 22 output resistance and line capacitance if low resistance metal lines are used.
The delay is represented by the equation:
D=Zdrv CT+(Rl Cl)/2 
where
D=delay,
Zdrv=output impedance of the driver,
CT=total capacitance seen by the driver,
R=resistance per unit length of the line of length, 1, and
C=capacitance per unit length of the line of length, 1.
Known techniques for minimizing clock skew are a tree type distribution system with buffers to drive short lines of equal length, and having all buffers on the same die as described in U.S. Pat. Nos. 5,586,307 and 4,860,322. Other known circuits include a daisy chain clock distribution network described in U.S. Pat. No. 5,546,023.
A circuit having lines of equal length is an H-tree distribution network illustrated in FIG. 2 for a 4xc3x974 array of cells to provide lines of equal length. The H-tree network has the property that the clock signal is delayed by an equal amount for each sub-block because all blocks are equidistant from the clock source.
L. Maliniak in xe2x80x9cDAC Attacks Designer Issuesxe2x80x9d, Electronic Design, vol. 43, p. 66, Jun. 12, 1995, describes other techniques for minimizing clock skew and delays including making some lines wider than others to increase the capacitance to account for the shorter lengths. Further, U.S. Pat. No. 5,307,381 provides a technique which uses buffers or drivers with various delays designed to compensate for different RC time constant delays and/or delays with can be varied by programming.
At higher clock speeds the inductance of even low resistance lines becomes important because the rise time on the waveforms approaches the transit time down the line, or transmission line effects become important. See A. Deutsch et al, xe2x80x9cWhen are Transmission-Line Effects Important for On-Chip Interconnections?xe2x80x9d, IEEE Trans. Microwave Theory and Techniques, vol. 45, No. 10, pp. 1836-1846, 1997.
Unfortunately such transmission lines use large voltage swings or voltage signaling, and cannot be terminated by a load resistor equal to the characteristic low impedance of the lines. As a result, reflections and ringing occurs which corrupts the clock signal. Also, large voltage signals and low impedance loads will result in excessive power consumption. See L. Maliniak, supra.
In accordance with the present invention, clock skew is avoided or at least minimized by changing the apparent length of transmission lines. The apparent length of a line is changed by adding capacitive and/or inductive elements to change the propagation constant and delay time of the line.
This is not the same technique as adding capacitance to RC dominated lines to change the time constant of the RC circuit. Adding capacitance to RC dominated lines serves to reduce the rise time or response time and further degrade the signal quality.
The capacitive and/or inductive elements are added in accordance with the present invention to change the propagation constant and delay time in the propagation of the signal down the line. Changing the delay time in this manner and by providing matched termination on the line cause the shape and quality of the signal to be maintained and only delays the signal in the time domain. In this manner the delay time along lines of different lengths are made to match and clock skews are eliminated or at least minimized. Conversely desired delays can be purposefully designed into the circuits to provide desired delay times between clocks and/or signals.
In accordance with the present invention, there is provided an integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.
The combination of low characteristic impedance transmission lines terminated in their characteristic impedance and current sense amplifiers which can discriminate against noise will result in well defined signals with well defined delays.
As used herein, xe2x80x9clow characteristic impedancexe2x80x9d means less than 100 ohms, and preferably less than 50 ohms.